CoolSem’s patented wafer-level thermal management technology helps chips run cooler, last longer, and perform beyond today’s limits.
CoolSem’s patented wafer-level thermal management technology helps chips run cooler, last longer, and perform beyond today’s limits.
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While traditional cooling techniques remove heat from the package or system level, the real challenge lies deeper.
In the thermal resistance of the chip’s substrate.



Active device

Substrate

heatsink
As devices cycle through temperature changes, the different materials inside each chip expand and contract at different rates — adding mechanical stress on top of thermal resistance. Over time, this stress degrades interfaces and compounds the very heat problem it’s meant to control.


Our wafer based solution
CoolSem removes the substrate, the barrier to efficient heat flow.
And we replace it with our patented wafer-level carrier that conducts heat up to 15× better.


Active Devices

Substrate

Waltis ®
WaLTIS® replaces the original substrate with a thinner, thermally optimized wafer-level stack, reducing thermal resistance by up to 15×. This helps lower peak device temperatures and mitigate thermal hotspots, while preserving existing device layouts and electrical isolation schemes.




WaLTIS directly targets the die-to-substrate bottleneck, lowering junction temperature and smoothing mechanical stress where GaN, GaAs, InP and SiC devices run hottest.
WaLTIS integrates after device fabrication, preserving existing SiC/GaN wafer lines while fitting seamlessly into today’s die-attach, DBC, and module assembly flows.
WaLTIS integrates with varied device types and manufacturing routes, enabling high-performance substrates without altering upstream designs or downstream assembly.
CoolSem develops wafer-levelthermal solutions for semiconductor and photonic devices.
Our WaLTIS technology replaces the original device substrate with an engineered thermal and mechanical stack designed to improve heat removal close to the active device layer. At the same time, it can help manage coefficient of thermal expansion (CTE) mismatch between the device and the next level in the assembly.
By improving this part of the thermal path, WaLTIS can support higher performance, greater reliability, longer lifetime and more efficient system-level cooling.
As semiconductor and photonic devices become more powerful and compact, heat and thermo-mechanical stress increasingly limit performance, reliability and integration.
High thermal resistance close to the active device can lead to higher operating temperatures, reduced efficiency, performance derating and greater demands on package- and system-level cooling. Differences in thermal expansion between materials can also create mechanical stress, particularly in larger dies, brittle semiconductor materials and applications exposed to repeated thermal cycling.
CoolSem addresses these challenges by improving the thermal and mechanical architecture at device level, close to where the heat is generated: Cool at the Core.
CoolSem addresses thermal performance at device level rather than relying only on improvements further downstream in the package or cooling system.
WaLTIS replaces the original device substrate after front-end fabrication with an engineered stack, designed specifically for the thermal, mechanical and electrical requirements of the final application.
This makes it possible to improve the first part of the thermal path, where significant bottlenecks can occur, while complementing existing package- and system-level cooling solutions.
WaLTIS is CoolSem's Wafer-Level Thermal Interface Stack. It is an engineered wafer-level substrate consisting of multiple functional layers. WaLTIS is bonded to a thinned customer wafer and is designed to provide four main functions: improved thermal conduction from the device layer to the next level in the assembly; better CTE matching to support mechanical stability under thermal cycling; electrical isolation where required, including for high-voltage and RF applications; and mechanical support for the resulting bonded wafer stack, which is especially relevant for brittle materials such as InP. CoolSem's first generation is aimed at wafer sizes up to 200 mm, with larger wafer formats to be addressed in the second generation and through licensing models.
WaLTIS is CoolSem's Wafer-Level Thermal Interface Stack: an engineered substrate that is integrated at wafer level after front-end device fabrication.
WaLTIS is bonded to a thinned device wafer and is designed to provide several functions within one integrated stack. Depending on the application, these can include improved thermal conduction, better CTE matching, electrical isolation and mechanical support.
By replacing the original device substrate with a stack optimized for the final application, WaLTIS improves the thermal and mechanical interface between the active device and the next level in the assembly.